1. Field
Example embodiments relate to semiconductor devices and methods of manufacturing the same, and more particularly, to buried channel array transistors (BCAT) and methods of manufacturing the same.
2. Description of the Related Art
As designs of manufactured semiconductor devices have been downsized and more highly-integrated over time, the pattern width associated with semiconductor devices has been reduced and the channel length has been shortened associated with semiconductor devices in cell transistors included in the semiconductor devices. In some cases, a difficulty associated with manufacturing semiconductor devices configured to obtain a sufficient refresh time of memory devices has increased due to a short channel effect that may result from reduced pattern width and channel length associated with the semiconductor devices.
A recess channel array transistor (RCAT) has been introduced for obtaining a sufficient effective channel length. In some example embodiments, the RCAT frequently fails by a high gate-induced drain leakage (GIDL). A buried channel array transistor (BCAT) has been proposed in such a way that the surface of the gate electrode is positioned below the surface of the silicon substrate to thereby reduce and/or minimize the GIDL of the RCAT.
In some example embodiments, the word lines of the BCAT tend to be arranged in a 6 F2 (F: minimum feature size) layout and the pitch of the word lines can be reduced to about 0.5 F, the occupation area of each cell transistor can be remarkably reduced using this arrangement. Accordingly, both of the effective channel length and the chip size can be reduced in memory devices by using the BCAT.